Today, the limiting factor for device performance is the transition time of
a signal in an IC. A key challenge for 0.1-mum technology is the interconn
ect delay, which can be reduced by the introduction of low-k dielectric and
copper. The integration of these interconnects need new lithographic strat
egies due to problems they entail. Therefore this paper deals with some iss
ues encountered during the hybrid lithography (e-beam-DUV) process for the
Trench First dual damascene structures. (C) 2001 Elsevier Science B.V. All
rights reserved.