An advanced image placement (IP) correction method that can compensate for
localized distortions was developed to improve the IP accuracy of X-ray mas
ks to the ultimate level. The method involves partitioning a chip into smal
l cells, and shifting the positions of the patterns in each cell to the ide
al ones that give the best IP accuracy. The amount of the shift is interpol
ated from the positions of the corners of cells. The expected attainable IP
accuracy was investigated by employing two kinds of interpolation function
s: a linear function and a 3rd-order spline function. It was found that lin
ear interpolation always gives the best results. This method was used to co
rrect the gate layer patterns of a 2-Gbit DRAM, and an IP accuracy of 3 sig
ma (X, Y) = (10.5 nm, 9.4 nm) was obtained. These values exceed the require
ments for the 100-nm technology node. (C) 2001 Published by Elsevier Scienc
e B.V.