Characterization of layer stacks in microelectronic products: Challenges to sample preparation and TEM analysis

Thin film and interface characterization are necessary in semiconductor ind ustry to ensure high yields and the required reliability of the products. P articularly, the analysis of layer stacks is a challenging task. Transmissi on electron microscopy (TEM) essentially contributes to layer stack analysi s in microelectronic products. Capabilities and limits of analytical TEM te chniques as well as advanced TEM sample preparation techniques are discusse d for front-end (MOS transistor) and back-end (interconnect) structures. Ty pical examples for advanced microprocessor devices are shown.