2 Gbit/s transimpedance amplifier fabricated by 0.35 mu m CMOS technologies

Citation
Cw. Kuo et al., 2 Gbit/s transimpedance amplifier fabricated by 0.35 mu m CMOS technologies, ELECTR LETT, 37(19), 2001, pp. 1158-1160
Citations number
5
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
ELECTRONICS LETTERS
ISSN journal
00135194 → ACNP
Volume
37
Issue
19
Year of publication
2001
Pages
1158 - 1160
Database
ISI
SICI code
0013-5194(20010913)37:19<1158:2GTAFB>2.0.ZU;2-W
Abstract
Integrated CMOS transimpedance, (TZ) amplifier circuits have been designed and fabricated based on a home-made BSIM model. A 0.35 mum CMOS technology was used for circuit realisation, and a capacitive-peaking design to improv e the bandwidth of the TZ amplifier is proposed and investigated. Using thi s approach provides an easy way to improve the performance of the TZ amplif ier; the measured 3 dB bandwidth is enhanced from 875 MHz to 1.35 GHz. The CMOS TZ amplifier design achieves a 2 Gbit/s data rate.