A 2-dB noise figure 900-MHz differential CMOS LNA

This paper proposes a new circuit topology for RF CMOS low noise amplifier (LNA). Since pMOS devices are approaching the performances of nMOS devices in scaled technologies, the idea is to realize the input stage shunting an inductively degenerated nMOS stage with a pMOS one. In this way, due to the inherent current reuse, the performances can be improved using the same po wer consumption. Since the devices of an inductively degenerated input stag e are working in moderate inversion (at least at moderate power dissipation ), prior to the stage optimization an appropriate moderate inversion model is introduced. A fully differential 900-MHz 0.35-mum CMOS LNA (plus output buffer) prototy pe achieves the following performances: 2-dB noise figure (NF), 17.5-dB pow er gain, -6-dBm IIP3 with 8-mA current consumption from a 2.7-V voltage sup ply. To the author's knowledge,, this is the lowest reported NF for a fully differential CMOS LNA operating at this power consumption level. As an add itional feature, this LNA has a programmable gain.