A fast-lock mixed-mode DLL using a 2-b SAR algorithm

In this paper, a fast-lock mixed-mode delay-locked loop (MMDLL) is presente d. The digital part of the MMDLL utilizes a 2-b SAR algorithm to achieve sh ort lock time compared to the conventional RDLL, CDLL, and SARDLL, while th e analog part helps to reduce the residue phase error introduced by the dig ital part and improve the output jitter performance. The measured RMS and p eak-to-peak jitters and the static phase error are 6.6, 47, and 12.4 ps, re spectively, for a 100-MHz input clock. The power consumption is 15.8 mW in the locked state at a 2.7-V supply voltage.. The maximum lock time is 13.5 clock cycles (135 ns) when the residue phase error is within 1LSB (156 ps).