An 8-bit 80-Msample/s pipelined analog-to-digital converter with background calibration

An 8-bit 80-Msample/s pipelined analog-to-digital converter (ADC) uses mono lithic background calibration to reduce the nonlinearity caused by intersta ge gain errors. Test results show that the ADC achieves a peak signal-to-no ise-and-distortion ratio of 43.8 dB, a peak integral nonlinearity of 0.51 l east significant bit (LSB), and a peak differential nonlinearity of 0.32 LS B with active background calibration. It dissipates 268 mW from a 3-V suppl y and occupies 10.3 mm(2) in a single-poly 0.5-mum CMOS technology.