A 2-V 300-MHz 1-Mb current-sensed double-density SRAM for low-power 0.3-mum CMOS/SIMOX ASICs

Silicon-on-insulator (SOI) devices have the great advantage of high operati ng speed in low supply voltages. This paper presents megabit-class high-spe ed and low-power embedded SRAM techniques for high data-throughput CMOS/SIM OX ASICs. In order to reduce the power dissipation of high-operating-freque ncy SRAMs, the multi-V-DD scheme using a low-voltage power supply only for restricted functional blocks is proposed along with the voltage-swing-match ing circuit for "low-voltage" blocks. A squashed double-density layout of s ix-transistor-type memory cell realizes a small size of 8.64 mum(2) under a 0.3-mum CMOS/SIMOX logic process including LOCOS isolation and plain local interconnections (e.g., tungsten-deposited diffusion layer and pseudoconta cts). A new resistor-coupled current-sense amplifier makes, it possible to detect the small readout signal from the memory cell with a short sensing t ime. To shorten the writing time, each bitline has an individual writing dr iver (per-bitline architecture). The recovery time of bitlines lowered to w rite data is also shortened with an accelerator combined with the pulse-res et wordline. A 64K-words x 16-bits SRAM test chip, fabricated with the 0.3- mum pseudomulti-V-th CMOS/SIMOX process (a short gate length of 0.2 mum is available for the fully depleted MOSFETs), has demonstrated the 300-MHz ope ration under a typical condition with 2- and 1-V power supplies. The power dissipation in standby is less than 0.1 mW and that at 200-MHz operation wi th a modified checkerboard test pattern is 35.6 mW for single fan-out loads .