SPICE modeling and quick estimation of MOSFET mismatch based on BSIM3 model and parametric tests

This paper reports a MOS transistor mismatch model applicable for submicron CMOS technologies and developed based on the industry standard BSIM3v3 mod el. A simple and unified expression was derived to formulate the effect of MOSFET mismatch on drain current variance. A way to quickly estimate the dr ain current mismatch was also suggested. The model has been integrated into HSPICE, and results obtained from simulation and measurements were compare d.