Using an optimized queueing network model to support wafer fab design

We develop an Optimized Queueing Network (OQNet) capacity planning tool for supporting the design of new and reconfigured semiconductor fabrication fa cilities that makes use of queueing network approximations and an optimizat ion routine. The basic problem addressed by this tool is to minimize the fa cility cost required to meet specified volume and cycle time targets. Featu res common to semiconductor environments, such as batch processes, re-entra nt flows, multiple product classes, and machine setups, are incorporated in to the model. Comparisons with simulation show that the queueing and other approximations are reasonably accurate. Tests of the optimization routine d emonstrate that it can find good solutions quickly.