CAM-BASED HIGHLY-PARALLEL IMAGE-PROCESSING HARDWARE

This paper describes content addressable memory (CAM)-based hardware t hat serves as a highly parallel, compact and real-time image-processin g system. The novel concept of a highly-parallel integrated circuits a nd system (HiPIC), in which a large-capacity CAM tuned for parallel da ta processing is a key element, is introduced. Several hardware algori thms for highly-parallel image processing based on a HiPIC with a CAM are presented in order to demonstrate that the HiPIC concept is effect ive for compact and rear-time image processing. Two kinds of HiPIC-ded icated CAM have been developed. One is embedded on a 0.5-mu m CMOS gat e array. An embedded CAM up to 64 kbit and logic up to 40 kgate can be integrated on a single chip. The other is a 0.5-/mu m CMOS full-custo m CAM LSI tuned for parallel data processing. A fully-parallel 336-kbi t CAM LSI has been successfully developed. The HiPIC concept and CAM-b ased hardware described here promises to be an important step towards the realization of a compact and real-time image-processing system.