AN ACCURATE MODEL OF FULLY-DEPLETED SURROUNDING GATE TRANSISTOR (FD-SGT)

A steady-state current-voltage characteristics of fully-depleted surro unding gate transistor (FD-SGT) is analyzed. First, the new gate oxide capacitance model and the new threshold voltage model of FD-SGT are p roposed. It is shown that the gate oxide capacitance per unit area inc reases with scaling down the silicon pillar's diameter. It is newly fo und that the threshold voltage decreases with scaling down the silicon pillar's diameter, because the gate oxide electric fields increase wi th increasing gate oxide capacitance. Next, by using the proposed mode ls, the new current-voltage characteristics equation of FD-SGT is anal ytically formulated for the first time. In comparison with the results of the three-dimensional (3D) device simulator, the results of the ne w threshold voltage model show good agreement within 0.012V error in m aximum. The results of the newly formulated current-voltage characteri stics also show good agreement within 1.4% average error. The results of this work make it possible to theoretically clear the device design s of FD-SGT and show the new viewpoints for future ULSI's with SGT.