SELF-LEARNING ANALOG NEURAL-NETWORK LSI WITH HIGH-RESOLUTION NONVOLATILE ANALOG MEMORY AND A PARTIALLY-SERIAL WEIGHT-UPDATE ARCHITECTURE

A self-learning analog neural network LSI with non-volatile analog mem ory which can be updated with more than 13-bit resolution has been des igned, fabricated and tested for the first time. The non-volatile memo ry is attained by a new floating-gate MOSFET device that has a charge injection part and an accumulation part separated by a high resistance . We also propose a partially-serial weight-update architecture in whi ch the plural synapse circuits use a weight-update circuit in common t o reduce the circuit area. A prototype chip fabricated using a 1.3-mu m double-poly CMOS process includes 50 synapse elements and its comput ational power is 10 MCPS. The weights can be updated at a rate of up t o 40 kHz. This chip can be used to implement backpropagation networks, deterministic Boltzmann machines, and Hopfield networks with Hebbian learning.