Adaptive routing on the new switch chip for IBM SP systems

The IBM RS/6000 SP is one of the most successful commercially available mul ticomputers. SP owes its success partially to the scalable. high bandwidth. low latency network. This paper describes the architecture of Switch2 swit ch chip, the recently developed third generation switching element which fu ture IBM RS/6000 SP systems may be based on. Switch2 offers significant enh ancements over the existing SP switch chips by incorporating advances in bo th VLSI technology and interconnection network research. One of the major n ew features of Switch2 is the incorporation of adaptive routing Support int o it. We describe the adaptive source routing architecture of the Switch2 c hip which is a unique feature of this chip. The performance of the adaptive source routing and oblivious routing for a wide range of system characteri stics and traffic patterns is evaluated. It is shown that adaptive Source r outing outperforms or performs comparably with oblivious routing. We propos e two novel algorithms for generating adaptive routes specifications requir ed for enabling the usage of adaptive source routing. A comparison between the cost of these two algorithms and the performance improvement obtained f ront using these algorithms are discussed. We also propose different Output Selection functions to be used in switching elements for implementing the adaptive routing. We evaluate and compare the performance of these selectio n functions and discover that the best selection functions for BMINs are no t dependent on the traffic pattern, message size, or system size. (C) 2001 Academic Press.