A NEW BIT TIMING RECOVERY SCHEME FOR HIGH BIT-RATE WIRELESS ACCESS

We propose a new bit timing recovery (BTR) scheme, what we call Step S ampled BTR (SSBTR), that can lower the sampling clock frequency and sh orten the clock phase convergence time, for burst signals in high bit rate wireless access systems. The SSBTR scheme has the following chara cteristics. A sine wave resulting from the BTR code passing through a Nyquist Transmission System is always used, the sampling clock has a l ower frequency than the system clock, and the clock phase of Intermedi ate Frequency (IF) signal input can be estimated from as few as 3 samp led data. The SSBTR scheme corrects the clock phase only once in a bur st signal. Therefore, in some wireless access systems, some kind of op eration must be performed after the SSBTR, in order to deal with long burst signals, instability of the system clock, and so on. In other wi reless access systems that do not have these problems, clock phase can be fixed by the SSBTR scheme alone. The performance of the SSBTR sche me with respect to additive white Gaussian noise (AWGN) was examined b y computer simulation. In addition, when SSBTR is implemented in hardw are, there are imperfections in the circuitry that lead to phase estim ation error and thus deterioration, so we studied the effects of sever al such imperfections by computer simulation. The results of these sim ulations clarify the performance of the SSBTR scheme.