Sub-60-nm quasi-planar FinFETs fabricated using a simplified process

N-channel double-gate metal-oxide-semiconductor field-effect transistor (MO SFET) FinFETs with gate and fin dimensions as small as 30 nm have been fabr icated using a new, simplified process. Short channel effects are effective ly suppressed when the Si fin width is less than two-thirds of the gate len gth. Drive current for typical devices is found to be above 500 muA/mum (or 1mA/mum, depending on the definition of the width of the double-gate devic e) for V-g - V-t = V-d = 1 V. The electrical gate oxide thickness in these devices is 21A, determined from the first FinFET capacitance-versus-voltage characteristics obtained to date. These results indicate that the FinFET i s a promising structure for the future manufacturing of integrated circuits with sub-60-nm feature size, and that double-gate MOSFETs can meet interna tional technology roadmap for semiconductors performance specifications wit hout aggressive scaling of the gate-oxide thickness.