Single chip video processor for digital HDTV

Citation
H. Yamauchi et al., Single chip video processor for digital HDTV, IEEE CONS E, 47(3), 2001, pp. 394-404
Citations number
1
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
IEEE TRANSACTIONS ON CONSUMER ELECTRONICS
ISSN journal
00983063 → ACNP
Volume
47
Issue
3
Year of publication
2001
Pages
394 - 404
Database
ISI
SICI code
0098-3063(200108)47:3<394:SCVPFD>2.0.ZU;2-Q
Abstract
We have developed a single chip video processor integrated TS decoder, MPEG 2 MP@HL decoder and OSD controller for BS digital broadcasting. The video p rocessor is available for all the formats of digital broadcasting and displ ays output on the "Hi-Vision" (high-definition) CRT in SDTV as well as HDTV . Also, 4-channel decoding/display and multi-angle broadcasting of digital TV is obtained. It has excellent functions such as seamless display, audio/ video (AV) synchronization, error concealment, etc. Adoption of cooperative processing architecture with hardware and software, pipeline architecture and parallel bus architecture allows flexible support of operating frequenc y reduction, circuit miniaturization, design simplification, high-performan ce service of BS digital TV, digital TV broadcasting regulation change and equipment specification change. This single chip video processor is manufac tured of 0.25-mum four-layer metal CMOS process and the chip size is 10.2 m m x 10.2 mm. The power consumption is 4.5 W when the supply voltage is 2.5 V and operating frequency is 121.5 MHz.