A memory efficient motion estimator for three step search block-matching algorithm

This paper describes a memory efficient array architecture with data-rings for the 3-step hierarchical search block-matching algorithm (3SHS). With th e efficient data-rings and memory organization, the regular raster-scanned data flow and comparator-tree structure can be used to simplify control sch eme and reduce latency, respectively. In addition, we utilize the three-hal f-search-area scheme and circular addressing method to reduce external memo ry access and memory size, respectively. The results demonstrate that the a rray architecture with memory efficient scheme requires a smaller memory si ze and low I/O bandwidth. It also provides a high normalized throughput sol ution for the 3SHS.