An efficient memory arbitration algorithm for a single chip MPEG2 AV decoder

Authors
Takizawa, T Hirasawa, M
Citation
T. Takizawa et M. Hirasawa, An efficient memory arbitration algorithm for a single chip MPEG2 AV decoder, IEEE CONS E, 47(3), 2001, pp. 660-665
Citations number
7
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
IEEE TRANSACTIONS ON CONSUMER ELECTRONICS
ISSN journal
00983063 → ACNP
Volume
47
Issue
3
Year of publication
2001
Pages
660 - 665
Database
ISI
SICI code
0098-3063(200108)47:3<660:AEMAAF>2.0.ZU;2-R
Abstract
This paper presents an efficient memory arbitration algorithm for system on a chip. We have implemented the algorithm into a single chip MPEG2 AV deco der. According to simulations, memory access efficiency of the arbiter base d on the new algorithm is around 95 % with a 32-bit 133 MHz SDRAM, while th ose of conventional arbiters are less than 80%.