This paper presents a quite comprehensive procedure covering both the stres
s-induced leakage current (SILC) and oxide breakdown, achieved by balancing
systematically the modeling and experimental works. The underlying model a
s quoted in the literature features three key parameters: the tunneling rel
axation time tau, the neutral electron trap density N-t, and the trap energ
y level E-t. First of all, 7-nm thick oxide MOS devices with wide range oxi
de areas are thoroughly characterized in terms of the optically induced tra
p filling, the charge-to-breakdown statistics, the gate voltage development
s with the time, and the SILC I-V. The former three are involved together w
ith a percolation oxide breakdown model to build N-t explicitly as function
of the stress electron fluence. Then the overall tunneling probability is
calculated, with which a best fitting to SILC I-V furnishes tau of 4.0 x 10
(-13) s and E-t of 3.4 eV. The extracted tau is found to match exactly that
extrapolated from existing data. Such striking consistencies thereby provi
de evidence that inelastic trap-assisted tunneling (ITAT) is indeed the SIL
C mechanism. Differences and similarities of the involved physical paramete
rs between different studies are compared as well.