Back-gate and series resistance effects in LDMOSFETs on SOI

Detailed experimental results are used to develop a new model for the linea r region of operation of lateral DMOSFETs (LDMOSFETs) on silicon-on-insulat or (SOI) that includes the influence of the buried oxide and back-gate. Bac k-gate biasing results in double-channel conduction and bias-dependent seri es resistance. Pertinent techniques for parameter extraction are presented and contrasted to those currently used in low-voltage SOI MOSFETs. The typi cal feature of LDMOSFETs is the significant change in series resistance as the back-gate is driven from accumulation to inversion. The model allows a clear identification of the architectural and technological parameters of t he device.