A nonseparable VLSI architecture for two-dimensional discrete periodized wavelet transform

Citation
Kc. Hung et al., A nonseparable VLSI architecture for two-dimensional discrete periodized wavelet transform, IEEE VLSI, 9(5), 2001, pp. 565-576
Citations number
23
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
ISSN journal
10638210 → ACNP
Volume
9
Issue
5
Year of publication
2001
Pages
565 - 576
Database
ISI
SICI code
1063-8210(200110)9:5<565:ANVAFT>2.0.ZU;2-U
Abstract
A modified two-dimensional (2-D) discrete periodized wavelet transform (DPW T) based on the homeomorphic high-pass filter and the 2-D operator correlat ion algorithm is developed in this paper. The advantages of this modified 2 -D DPWT are that it can reduce the multiplication counts and the complexity of boundary data processing in comparison to other conventional 2-D DPWT f or perfect reconstruction. In addition, a parallel-pipeline architecture of the nonseparable computation algorithm is also proposed to implement this modified 2-D DPWT. This architecture has properties of noninterleaving inpu t data, short bus width request, and short latency. The analysis of the fin ite precision performance shows that nearly half of the bit length can be s aved by using this nonseparable, computation algorithm. The operation of th e boundary data processing is also described in detail. In the three-stage decomposition of an N x N image, the latency is found to be N-2 + 2N + 18.