Two new techniques for mapping circuits are proposed in this paper. The fir
st method, called the odd-level transistor replacement (OTR) method, has a
goal that is similar to that of technology mapping, but without the restric
tion of a fixed library size and maps a circuit to a virtual library of com
plex static CMOS gates. The second technique, the static CMOS/pass transist
or logic (PTL) method, uses a mix of static CMOS and PTL to realize the cir
cuit and utilizes the relation between PTL and binary decision diagrams. Th
e methods are very efficient and can handle all of the ISCAS'85 benchmark c
ircuits in minutes. A comparison of the results with traditional technology
mapping using SIS on different libraries shows an average delay reduction
above 18% for OTR, and an average delay reduction above 35% for the static
CMOS/PTL method, with significant savings in the area.