On gate level power optimization using dual-supply voltages

In this paper, we present an approach for applying two supply voltages to o ptimize power in CMOS digital circuits under the timing constraints. Given a technology-mapped network, we first analyze the power/delay model and the timing slack distribution in the network. Then a new strategy is developed for timing-constrained optimization issues by making full use of slacks. B ased on this strategy, the power reduction is translated into the polynomia l-time-solvable maximal-weighted-independent-set problem on transitive grap hs. Since different supply voltages used in the circuit lead to totally dif ferent power consumption, we propose a fast heuristic approach to predict t he optimum dual-supply voltages by looking at the lower bound of power cons umption in the given circuit. To deal with the possible power penalty due t o the level converters at the interface of different supply voltages, we us e a "constrained F-M" algorithm to minimize the number of level converters. We have implemented our approach under SIS environment. Experiment shows t hat the resulting lower bound of power is tight for most circuits and that the predicted "optimum" supply voltages are exactly or very close to the be st choice of actual ones. The total power saving of up to 26% (average of a bout 20%) is achieved without degrading the circuit performance, compared t o the average power improvement of about 7% by gate sizing technique based on a standard cell library. Our technique provides the power-delay tradeoff by specifying different timing constraints in circuits for power optimizat ion.