On effective I-DDQ testing of low-voltage CMOS circuits using leakage control techniques

The use of low-threshold devices in low-voltage CMOS circuits leads to an e xponential increase in the intrinsic leakage current. This threatens the ef fectiveness Of I-DDQ testing for such low-voltage circuits because it is di fficult to differentiate a defect-free circuit from defective circuits. Rec ently, several leakage control techniques have been proposed to reduce intr insic leakage current, which may benefit I-DDQ testing. In this paper, we i nvestigate the possibilities of applying different leakage control techniqu es to improve the fault coverage Of I-DDQ testing. Results on a large numbe r of benchmarks indicate that dual-threshold and vector control techniques can be very effective in improving fault coverage for I-DDQ testing for som e circuits.