A cost-effective design for MPEG-2 audio decoder with embedded RISC core

MPEG-2 audio decoding algorithms are involved of several complex coding tec hniques and therefore difficult to be implemented by an efficient dedicated architecture design. In this paper, we present an effective architecture f or the MPEG-2 audio decoder. The MPEG-2 audio algorithms can be roughly div ided into two types of operations. The first type is regular but computatio n-intensive such as filtering, matrixing, degrouping, and transformation op erations. The second type is not regular but computation-intensive such as parsing bitstream, setting operation mode and controlling of all system ope rations. A RISC core with variable instruction length is designed for the d ecision-making part, and the dedicated hardware such as special divider, an d synthesis filterbank is designed for the computation-intensive part. Base d on the standard cell design technique, the VLSI chip consists of 27000 ga te counts with the chip size of 6.4 x 6.4 mm(2). The chip can run at maximu m 43.5 MHz clock rate, with the power dissipation of 150 mW at 3 V power su pply.