Substrate engineering to improve soft-error-rate immunity for SRAM technologies

We present experimental as well as simulation data which emphasizes the imp act of the well and substrate architecture for the charge collection effici ency during an alpha particle hit. Several different SRAM cores with implan ted buried layer, epitaxial grown and standard CZ substrates are subjected to alpha-particle events and the soft error rate is recorded. The best SER immunity was achieved with the standard CZ substrate. This findings are con tradictive to earlier reports for DRAM memory cores and will be explained i n detail within this paper. Resulting from this analysis-we optimize the su bstrate to improve the SER immunity of SRAM cores by engineering the nwell tub. There is a strong dependence of SER immunity and nwell-to-nwell spacin g. Several different SRAM cores are analyzed with respect to optimizing the nwell spacing. (C) 2001 Elsevier Science Ltd. All rights reserved.