Wafer level accelerated test for ionic contamination control on VDMOS transistors in bipolar/CMOS/DMOS

This paper presents results of an accelerated test for ionic contamination measurement, at wafer level, on VDMOS transistors in Bipolar/CMOS/DMOS tech nology. This test is performed at 300 degreesC during 4 hours with voltage stress on metal 2 plate. The ionic contamination level is obtained by the m easurements of DC parameters: threshold voltage and maximum of transconduct ance in linear region, monitored with HP4145B Semiconductor Parameter Analy ser. In comparison with high temperature reverse bias (at 150 degreesC 1000 h) necessary for product qualification test on packaged components, this ac celerated test can assure an ionic contamination periodical control adapted for wafer level reliability. (C) 2001 Elsevier Science Ltd. All rights res erved.