Polysilicon oxide quality optimization at wafer level of a Bipolar/CMOS/DMOS technology

Inter-polycrystalline silicon oxide capacitor, further called, "polysilicon oxide", is one of the peculiarities of Bipolar/CMOS/DMOS process. The oxid ation of polycrystalline silicon generates poor polysilicon/oxide interface quality, in comparison with mono-crystalline silicon one, because differen t ratios of oxidation exist between grains and grains boundaries. This impl ies a decreasing of the oxide strength from 10 MV/cm (oxide on mono-crystal line silicon and same thickness) to 7 MV/cm. The optimization of this oxide needs specific approaches of process and of reliability test. After presen tation of polysilicon oxide process, this paper deals with optimization of the quality of this oxide using several approaches and tested at wafer leve l with specific test masks. To shorten the quality evaluation measurement o f this oxide, a correlation between voltage and breakdown electrical field is established and discussed; this correlation allows establishing a rapid wafer level estimation at parametric test level and acts as a quality indic ator. This wafer level techniques is applied on Bipolar/CMOS/DMOS technolog y. (C) 2001 Elsevier Science Ltd. All rights reserved.