An overview of hot-carrier induced degradation in 0.25 mu m Partially and Fully Depleted SOIN-MOSFET's

Hot-carrier induced degradation was performed on 0.25 mum long and 40 mum w ide Partially Depleted (PD) and Fully Depleted (FD) SOI N-MOSFET's with LDD drain architecture. They underwent accelerated electrical stress degradati on by applying different front & back gate biases as well as drain voltages to obtain reasonable stress duration, and to present significant variation s of the main electrical parameters such as the threshold voltage or the ma ximal trans conductance. The aim of this paper is to look after the worst-c ase aging, and to focus on the extrapolation of the device lifetime in thes e conditions. (C) 2001 Elsevier Science Ltd. All rights reserved.