Copper and low dielectric constantant (k) materials are poised to become th
e dominant interconnect scheme for integrated circuits for the future becau
se of the low resistance and capacitance that they offer which can improve
circuit performance by more than 30% over conventional interconnect schemes
. This paper addresses the thermo mechanical stresses in the Cu/low-k inter
connect schemes through numerical simulation and identifies the locations o
f maximum stress in the structure with view to providing information on the
impact that different dielectric materials have on the stress distribution
in the interfaces between metals and dielectric layers. (C) 2001 Elsevier
Science Ltd. All rights reserved.