On development of 6H-SiC LDMOS transistors using silane-ambient implant anneal

6H-SiC lateral double implanted metal oxide semiconductor field effect tran sistors have been fabricated on four p-type wafers with p-type epitaxial la yers doped with Al at 2-7 x 10(16) cm(-3). Each of the wafers received two nitrogen implants of heavy and light doses for drain/source and drift regio ns, respectively. The wafers had the implants activated at 1600 degreesC in an Ar ambient (one wafer) or a silane overpressure ambient (three wafers). The subsequent characterization confirmed a much smoother surface for the silane-annealed wafers, with step bunching reduced from 25 nm peak steps wi th periodicity of 1 mum to undetectable steps. Near optimal breakdown volta ges of 600 V were obtained for a 9 mum drift region length devices, and thr eshold voltage ranged from 9 to 12 V. Average values for effective channel mobility mu (eff) were in the range 35.2-44.1 cm(2)/Vs for the three silane -annealed wafers, and 30.0 cm(2)/Vs for the argon-annealed wafer. (C) 2001 Elsevier Science Ltd. All rights reserved.