An RF power amplifier in a digital CMOS process

A two stage class B power amplifier for 1.9 GHz is presented. The amplifier is fabricated in a standard digital EPI-CMOS process with low resistivity substrate. The measured output power is 29 dBm in a 50 Omega load. A design method to find the large signal parameters of the output transistor is pre sented. It separates the determination of the optimal load resistance and t he determination of the large signal drain-source capacitance. Based on thi s method, proper values for on-chip interstage matching and off-chip output matching can be derived. A envelope linearisation circuit for the PA is pr oposed. Simulations and measurements of a fabricated linearisation circuit are presented and used to calculate the achievable linearity in terms of th e spectral leakage and the error vector magnitude of a EDGE (3 pi /8-8PSK) modulated signal.