Defect engineering in annealed n-type GaAs epilayers using SiO2/Si3N4 stacking layers

We have used SiO2/Si3N4 stacking layers to control the creation of defects in rapid thermally annealed epitaxial GaAs layers. Annealing at 900 degrees C introduces three electron traps S1 (E-c-0.23 eV), S2 (E-c-0.53 eV), and S 4 (E-c-0.74 eV) in SiO2/n-GaAs. The concentrations of S1 and S4 decreased b y factors of similar to 28 and similar to 19, respectively, in Si3N4/SiO2/n -GaAs. The overlap of a hole trap with the S2 peak in Si3N4/SiO2/n-GaAs res ults in an apparent decrease in the concentration of S2 by over two orders of magnitude. The lower concentration of defects in the region probed by de ep level transient spectroscopy is explained by the tensile stress which th e Si3N4 layer imposes on the structure during annealing. In addition to S1 and S4, hole traps H1 (E-v+0.28 eV) and H2 (E-v+0.42 eV) are observed in Si 3N4/n-GaAs and SiO2/Si3N4/n-GaAs, respectively. The concentration of defect s is larger by similar to1.5 times in the latter structure. SiO2/Si3N4 stac king layers can, therefore, be used to achieve spatially selective modifica tion of GaAs-based structures using defect engineering. (C) 2001 American I nstitute of Physics.