Approaches to low-power implementations of DSP systems

Reduction of power consumption is significantly important for all high-perf ormance digital VLSI systems. This paper reviews several approaches for low -power implementations of building blocks for digital subscriber line (DSL) systems. Low-power implementations of Reed-Solomon (RS) coders, fast Fouri er transforms (FFTs), FIR filters, and equalizers, and reduction of power c onsumption by use of dual supply voltages are addressed. It is shown that u se of separate Galois Field functional units for multiply-accumulate and de gree reduction can reduce the energy consumption of RS coders dramatically. A hybrid feedforward and feedback commutator scheme-based FFT is shown to require less area and fall hardware utilization efficiency. Reduction of sw itching activity at one or both inputs of the multipliers is a key to reduc tion of power consumption in FIR filters and equalizers. The switching acti vity can be reduced by use of transpose structure and by time-multiplexing of an unfolded filter. A well established retiming approach can be generali zed to find those noncritical gates which can be operated with lower supply voltages to reduce the overall system power consumption.