Low trap density nonleaky SiGe quantum well MOS structures - Fabrication and characteristics

SiGe quantum well metal-oxide-semiconductor (MOS) structures were fabricate d by low pressure chemical vapor deposition of the epitaxial layers, or by molecular beam epitaxy (MBE), followed by thermal oxidation of the silicon cap layer at 1100 degreesC. Examined were the effects of the quantum layer composition, the epitaxy technique, the pre-oxidation surface preparation, the oxidation temperature, and the annealing conditions, on the device qual ity and the strain relaxation. Addition of Ge to the quantum well was found to increase the interface trap density, due possibly to an increase in the lattice strain, while the addition of C resulted in a reduction of the tra p density, due possibly to a decrease in the lattice strain as well as pass ivation of the traps at the Si-SiO2 interface by C. The interface trap dens ity was higher in the case of MBE epi layers, perhaps, due to metal contami nation of the samples by the MBE growth chamber. The lowest interface trap densities [2-8 x 10(10)/cm(2) V] and the lowest oxide leakage current densi ties [<10-(11) A/cm(2) over a range of -2.5 to 1.0 V] were obtained in the case of rapid thermal oxidation at 1100<degrees>C, without my relaxation of the strained SiGe or SiGeC layer. (C) 2001 The Electrochemical Society.