A study of hot-carrier induced interface-trap profiles in lateral asymmetric channel MOSFETs using a novel charge pumping technique

The spatial distribution of interface traps in hot-carrier stressed lateral asymmetric channel (LAC) and conventional (CON) MOSFETs have been determin ed using a novel charge pumping technique. Detailed post-stress interface c haracterization shows reduced interface-trap buildup and lesser drain curre nt degradation in LAC MOSFETs compared to the CON device, for stressing at different times and drain biases and for all channel lengths down to 100 mn . The interface-trap profile parameters (peak magnitude and spread) have be en correlated to drain current degradation as function of stress drain bias and time. It is shown that with increased stress drain bias and time, both the peak and spread of the interface-trap profiles increase, but at differ ent rates. While the peaks evolve identically for CON and LAC MOSFET's, the spreads do not, which is shown to affect the rate of the resulting transco nductance degradation differently. Device simulations show a lower peak lat eral electric field in LAC MOSFETs compared to CON devices, which is respon sible for the observed reduction in hot-carrier degradation in such devices . (C) 2001 Elsevier Science Ltd. All rights reserved.