Design considerations for 25 nm MOSFET devices

This paper presents the results of a systematic theoretical investigation o n scaling gate oxide thickness and the source-drain extension (SIDE) juncti on depth to design high performance MOSFET devices with effective channel l engths near 25 nm. In order to obtain 25 mn MOSFETs, CMOS technologies with 40, 50, and 60 mn gate lengths were designed by scaling SDE junction depth to 14, 20, and 26 nm, respectively. Each technology with the target gate o xide thickness was optimized for an off-state leakage current similar to 10 nA/mum for 25 nm devices and the device characteristics were obtained for an equivalent gate oxide thickness of 1, 1.5, and 2 nm. The results show th at for a target off-state leakage current of 25 run. devices the magnitude of threshold voltage, sub-threshold slope, and drain-induced barrier loweri ng increases while the magnitude of drive current decreases with the increa se of gate oxide thickness. On the other hand, the variation in the magnitu de of threshold voltage, sub-threshold slope, drain-induced barrier lowerin g, and the drive current for the similar devices is insignificant within th e range of SDE junction depth 14-26 nm. It is, also, found that the gate de lay for 25 nm devices increases with the increase of SDE junction depth. Th is study, clearly, demonstrates the importance of scaling gate oxide thickn ess and the SDE junction depth below the presently reported limits to desig n high performance 25 nm MOSFET devices for low voltage application. (C) 20 01 Elsevier Science Ltd. All rights reserved.