A bus delay reduction technique considering crosstalk

Recently, progress in shrinking CMOS process technology and increasing chip size has made interconnect delay. a serious problem in deep micron LSI des ign. The interconnect delay is maximized by the influence of crosstalk when adjacent wires simultaneously switch in opposite transient directions. Thi s paper proposes an on-chip bus delay reduction technique based on shifting the signal transition timing of adjacent wires. From an equation for the a pproximate bus delay, delay reduction can be achieved by applying the propo sed technique to repeater-inserted on-chip buses. The result of SPICE simul ation also shows that at most a 20% reduction of the total bus delay can be achieved. (C) 2001 Scripta Technica.