Fast closed-loop-power-control (CLPC) plays a key role in direct-sequence (
DS) code division multiple access (CDMA) systems, aiming at achieving accep
table carrier-to-interference (C/I) ratios in all active links. Assuming a
terrestrial mobile access, where the round-trip delay may be smaller than t
he channel time-coherence, fast CLPC can compensate for fading and reduce t
he error burstiness, as well. This paper provides analytical expressions fo
r the bit error probability given: the CLPC algorithm specified in terms of
loop delay and updating rate, the propagation power-delay-profile and the
terminal speed. A binary PSK DS spread spectrum radio interface, with rake
processing of multipath or diversity, is considered. Our link-level analysi
s, being conditioned to a specified average value of CII, is focused on the
inverse update algorithm, which is aimed at keeping the received power at
a constant level. Applications of the derived method, aimed at getting insi
ght about CLPC performance in 3rd generation radio interfaces, is also prov
ided and discussed.