A low-power 10-bit ADC in a 0.25-mu m CMOS: Design considerations and testresults

This paper presents the design and test of a low power analog-to-digital co nverter (ADC) implemented in a commercial 0.25 mum CMOS technology. The cir cuit has been developed to serve as a building block in multichannel data a cquisition systems for high energy physics (HEP) applications. Therefore, m edium resolution (10 bits), very low power consumption, and high modularity are the key features of the design. In HEP experiments, the resistance of the electronics to the ionizing radiation is often a primary issue. Hence, the ADC has been laid out using a radiation-tolerant approach. The test res ults show that the chip operates as a full 10-bit converter up to a clock f requency of 30 MHz. No degradation in performance has been measured after a total dose of 10 Mrd (SiO2).