A multibitrate burst-mode CDR circuit with bit-rate discrimination function from 52 to 1244 Mb/s

In this letter, we fabricate and assess a clock and data recovery (CDR) cir cuit with a bit-rate discrimination (BRD) function that can receive burst-m ode signals containing packets of different bit rates. The clock recovery c ircuit in the CDR circuit consists of gated oscillators (GOs) for handling the burst-mode signals, whose bit rates vary with each packet. Moreover, we improve the performance of the clock recovery circuit based on GOs against the bit rate unevenness around each bit rate. By combining an agile clock recovery circuit and a digital BRD circuit, the CDR circuit can handle mult iplexed bit rates. Tests show that the circuit offers excellent performance for the multiplexed bit rates of nonreturn-to-zero 52, 155, 622, and 1244 Mb/s.