Performance and power effectiveness in embedded processors - Customizable partitioned caches

This paper explores an application-specific customization technique for the data cache, one of the foremost area/power consuming and performance deter mining microarchitectural features of modern embedded processors. The autom ated methodology for customizing the processor microarchitecture that we pr opose results in increased performance, reduced power consumption and impro ved determinism of critical system parts while the fixed design ensures pro cessor standardization. The resulting improvements help to enlarge the sign ificant role of embedded processors in modern hardware-software codesign te chniques by leading to increased processor utilization and reduced hardware cost. A novel methodology for static analysis and a microarchitecturally f ield-reprogrammable implementation of a customizable cache controller that implements a partitioned cache structure is proposed. Partitioning the load /store instructions eliminates cache interference; hence, precise knowledge about the hit/miss behavior of the references within each partition become s available, resulting in significant reduction in tag reads and comparison s. Moreover, eliminating cache interference naturally leads to a significan t reduction in the miss rate. The paper presents an algorithm for defining cache partitions, hardware support for customizable cache partitions, and a set of experimental results. The experimental results indicate significant improvements in both power consumption and miss rate.