A retargetable VLIW compiler framework for DSPs with instruction-level parallelism

A standard design methodology for embedded processors today is the system-o n-a-chip design with potentially multiple heterogeneous processing elements on a chip, such as a very long instruction word (VLIW) processor, digital signal processor (DSP), and field-programmable gate array. To be able to pr ogram these devices, we need compilers that are capable of generating effic ient code for the different types of processing elements with efficiency me asured in terms of power, area, and execution time. In addition, the compil ers should also be highly retargetable to enable the system designer to qui ckly evaluate different cores for the application on hand and reduce the ti me to market. In this paper, we show that we can extend a conventional VLIW compilation environment to develop highly retargetable optimizing compiler s for DSPs with irregular architectures. We have used the second generation Fujitsu Hiperion fixed-point DSP as our primary example to evaluate the co mpiler framework. We demonstrate through experimental results that executio n time for the assembly code generated using our framework is roughly two t imes better than that of the code generated by a widely used commercially a vailable DSP compiler. Even without incorporating DSP-specific optimization s in our extended VLIW framework, we demonstrate that the compiled code has a better performance than the code generated by a commercial DSP-specific compiler in all our examples.