Delay fault testing: Choosing between random SIC and random MIC test sequences

The combination of higher quality requirements and sensitivity of high perf ormance circuits to delay defects has led to an increasing emphasis on dela y testing of VLSI circuits. In this context, it has been proven that Single Input Change (SIC) test sequences are more effective than classical Multip le Input Change (MIC) test sequences when a high robust delay fault coverag e is targeted. In this paper, we show that random SIC (RSIC) test sequences achieve a higher fault coverage than random MIC (RMIC) test sequences when both robust and non-robust tests are under consideration. Experimental res ults given in this paper are based on a software generation of RSIC test se quences that can be easily generated in this case. For a built-in self-test (BIST) purpose, hardware generated RSIC sequences have to be used. This ki nd of generation will be shortly discussed at the end of the paper.