Optimizing sinusoidal histogram test for low cost ADC BIST

The histogram method is a very classical test technique for Analog to Digit al Converters (ADCs), but only used for external testing because of the lar ge amount of required hardware resources. This paper discusses the viabilit y of a BIST implementation for this technique. An original approach is deve loped that permits to extract the ADC parameters with a reduced area overhe ad. This approach involves (i) the calculation of the parameters using appr oximations and (ii) the decomposition of the global test in a code-after-co de test procedure. These two features allow a significant reduction of the required operative resources and memory dedicated to the storage of experim ental data. In addition, the use of a piece-wise approximation for computin g the ideal histogram also permits to minimize the memory dedicated to the storage of reference data.