A discussion on test pattern generation for FPGA - Implemented circuits

The objective of this paper is to generate a Application-Oriented Test Proc edure to be used by a FPGA user in a given application. General definitions concerning the specific problem of testing RAM-based FPGAs are first given such as the important concept of 'AC-non-redundant fault.' Using a set of circuits implemented on a XILINX 4000E, it is shown that a classical test p attern generation performed on the circuit netlist gives a low AC-non-redun dant fault coverage and it is pointed out that test pattern generation perf ormed on a FPGA representation is required. It is then demonstrated that te st pattern generation performed on the FPGA representation can be significa ntly accelerated by removing most of the AC-redundant faults. Finally, a te chnique is proposed to even more accelerate the test pattern generation pro cess by using a reduced FPGA description.