Charge-loss effects in device dielectric strongly limit the reliability of
non-volatile memory cells. The explanation of the leakage mechanisms is the
refore an essential condition for the establishment of scaled and reliable
technology for data storage, This paper concerns with the physical interpre
tation of the stress-induced leakage current (SILC), based on both experime
ntal and computational investigations on MOS capacitor structures. It is fo
und that: (a) the leakage is partly due to electron-hole recombination mech
anisms in the bulk oxide, (b) defect levels acting as recombination- and tr
ap-assisted tunneling (RTAT) sites are located at deep energy levels in the
SiO2 and (c) the SILC characteristics of thin oxide (t(ox) < 8.5 nm) MOS s
amples can be very well reproduced by a numerical model featuring RTAT as t
he leading mechanism of the leakage. As a result, the oxide-degradation eff
ects can be monitored by the new numerical tool. (C) 2001 Elsevier Science
Ltd. All rights reserved.