Design-form-reusability in VHDL

The reuse of electronic components can improve productivity in system desig n. However, without careful planning, components are rarely designed for re use. Hardware description languages are commonly used to construct from sim ple hardware to complex ones. HDLs allow the creation of reusable models, b ut the reusability of a design does not come with language features alone. It requires design disciplines to reach an efficient reusable design. Reusa bility issues and design methodologies to achieve design-for-reusability (D FR) are presented. Results of measuring the reusability of ten VHDL applica tions, based on the proposed reusable models, are summarised. This research allows us to gain an insight into DFR.