56 Gbit/s analogue PLL for clock recovery

A clock-recovery circuit is reported that employs a phase-locked. loop (PLL ) at 56.88 Gbit/s. and is demonstrate by locking to a 28.44 GHz sinosoidal signal while two additional circuits with adapted on-chip passive component s are locked to 29 and 39 Gbit/s pseudorandom bit sequences, To the knowled ge of the authors, this is the First demonstration of an integrated PLL int egrated circuit for clock recovery at a data rate well above 40 Gbit/s.